module register(q, qbar, preset, clear, write, clock,d);
	input preset, clear, write, clock;
	input [31:0] d;
	output [31:0] q, qbar;
	
	dffpc r0 (q[0],qbar[0],preset,clear,write,clock,d[0]);
	dffpc r1 (q[1],qbar[1],preset,clear,write,clock,d[1]);
	dffpc r2 (q[2],qbar[2],preset,clear,write,clock,d[2]);
	dffpc r3 (q[3],qbar[3],preset,clear,write,clock,d[3]);
	dffpc r4 (q[4],qbar[4],preset,clear,write,clock,d[4]);
	dffpc r5 (q[5],qbar[5],preset,clear,write,clock,d[5]);
	dffpc r6 (q[6],qbar[6],preset,clear,write,clock,d[6]);
	dffpc r7 (q[7],qbar[7],preset,clear,write,clock,d[7]);
	dffpc r8 (q[8],qbar[8],preset,clear,write,clock,d[8]);
	dffpc r9 (q[9],qbar[9],preset,clear,write,clock,d[9]);
	dffpc r10 (q[10],qbar[0],preset,clear,write,clock,d[10]);
	dffpc r11 (q[11],qbar[0],preset,clear,write,clock,d[11]);
	dffpc r12 (q[12],qbar[0],preset,clear,write,clock,d[12]);
	dffpc r13 (q[13],qbar[0],preset,clear,write,clock,d[13]);
	dffpc r14 (q[14],qbar[0],preset,clear,write,clock,d[14]);
	dffpc r15 (q[15],qbar[0],preset,clear,write,clock,d[15]);
	dffpc r16 (q[16],qbar[0],preset,clear,write,clock,d[16]);
	dffpc r17 (q[17],qbar[0],preset,clear,write,clock,d[17]);
	dffpc r18 (q[18],qbar[0],preset,clear,write,clock,d[18]);
	dffpc r19 (q[19],qbar[0],preset,clear,write,clock,d[19]);
	dffpc r20 (q[20],qbar[0],preset,clear,write,clock,d[20]);
	dffpc r21 (q[21],qbar[0],preset,clear,write,clock,d[21]);
	dffpc r22 (q[22],qbar[0],preset,clear,write,clock,d[22]);
	dffpc r23 (q[23],qbar[0],preset,clear,write,clock,d[23]);
	dffpc r24 (q[24],qbar[24],preset,clear,write,clock,d[24]);
	dffpc r25 (q[25],qbar[25],preset,clear,write,clock,d[25]);
	dffpc r26 (q[26],qbar[26],preset,clear,write,clock,d[26]);
	dffpc r27 (q[27],qbar[27],preset,clear,write,clock,d[27]);
	dffpc r28 (q[28],qbar[28],preset,clear,write,clock,d[28]);
	dffpc r29 (q[29],qbar[29],preset,clear,write,clock,d[29]);
	dffpc r30 (q[30],qbar[30],preset,clear,write,clock,d[30]);
	dffpc r31 (q[31],qbar[31],preset,clear,write,clock,d[31]);

endmodule

module dffpc(q, qbar, preset, clear, write, clock,d);
	input preset,clear,clock,d, write;
	output q, qbar;
	wire cbar,w0,w1;
	reg q, qbar;
	
	always @(preset or clear or negedge clock or write)
	begin
		case(write)
			1'b1:begin
				case(d)
					1'b0:begin q = 0; qbar = 1; end
					1'b1:begin q = 1; qbar = 0; end
				endcase
				end
		endcase
		case(preset)
			1'b1:begin q = 1; qbar = 0; end
		endcase
		case(clear)
			1'b1:begin q = 0; qbar = 1; end
		endcase
	end
	
endmodule
/*
module m555(clock);
    parameter InitDelay = 5, Ton = 50, Toff = 50;
    output clock;
    reg clock;

    initial begin
        #InitDelay clock = 1;
    end

    always begin
        #Ton clock = ~clock;
        #Toff clock = ~clock;
    end
endmodule

module testD(q, qbar, preset, clear, write, clock, data);
    input  clock;
	input [31:0] q, qbar;
    output preset, clear, write;
	output [31:0] data;
    reg    preset, clear, write;
	reg [31:0] data;

    initial begin
        $monitor ($time, " q= %d, clock= %d, data= %d, preset= %d, clear= %d, write= %d", q, clock, data,preset,clear, write);
        data = 0;
		#25 preset = 0; clear = 0; write = 1;
		#50 preset = 0; clear = 0; write = 1;
        #100  data = 32'd53; preset = 0; clear = 0; write = 1;
        #100 data = 32'd654; preset = 0;
		#100 clear = 0; preset = 1;
		#100 clear = 0; preset = 0;
        #100 data = 32'd468432; preset = 0;
        #100 data = 0;
        #100 $finish; /* $finish simulation after 100 time simulation units *//*
    end
endmodule

module testBenchD;
    wire clock, preset, clear, write;
	wire [31:0] q, qbar, data;
    m555 clk(clock);
    register dl(q, qbar, preset, clear, write, clock, data);
    testD td(q, qbar, preset, clear, write, clock, data);
endmodule*/
